FPGA Based Adujsted Step Size LMS Algorithm for Adaptive Noise Cancellation
In this paper an FPGA based Adaptive Noise Canceller (ANC) with two inputs was designed and built using our previously proposed algorithm in 2014, which was called Absolute Average Error Adjusted Step Size LMS (AAE-ASSLMS). This algorithm is synthesized and simulated on Xilinx Spartan-3E platform. Then a connection between MATLAB and FPGA was made in order to solve the problem of entering the speech signal to FPGA for testing the FPGA performance with perfect appearance. A comparison between hardware and MATLAB software implementation is then made and the results were approximately equal. The suggested AAE-ASSLMS adaptive filter that implemented on FPGA for ANC application works well. The final hardware design can be used for the embedded applications as System on Chip (SoC) for ANC in many portable applications like mobile phone and hearing aids.